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King Billion Electronics Co., Ltd
- Table of Contents -
1. 2. 3. 4. 5. 6.
HF88M32B
General Description_______________________________________________________________2 Features ________________________________________________________________________2 Functional block diagram __________________________________________________________3 Pin Description __________________________________________________________________3 Pad Location ____________________________________________________________________5 Device Operation _________________________________________________________________6
6.1. 6.2. 6.3. 6.4. 6.5. 6.6. Retrieve data in Data File ____________________________________________________________8 Loading the Address Counter _________________________________________________________8 Sequential Read Mode and Auto Increment of Address Counter ____________________________8 Output data to External I/O __________________________________________________________9 Reading Input pin status _____________________________________________________________9 Retrieving the Contents of Extension I/O registers________________________________________9
7.
Timing Diagrams _________________________________________________________________9
7.1. 7.2. 7.3. 7.4. 7.5. 7.6. Data File Read Cycle _______________________________________________________________10 Interrupted by I/O when Loading Address Counter______________________________________11 Setting and Reading the I/O Mode for P0 and P1 ________________________________________11 Reading P0 and P1 in Mixed-I/O Mode ________________________________________________12 Reading the input pins ______________________________________________________________12 Output to P0 and P1 Ports___________________________________________________________13
8. 9. 10. 11.
Absolute Maximum Rating ________________________________________________________13 AC/DC Electrical Characteristics ___________________________________________________13 Application Circuit Diagram _____________________________________________________14 Updated History _______________________________________________________________15
January 16, 2004
1
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King Billion Electronics Co., Ltd

HF88M32B
1. General Description
The HF88M32B is a command interfaced 4M x 8 bit Mask ROM. It features command mode interface with external CPU or MCU. In other words, it uses only 8-bit data bus and a few additional control pins to load addresses and provide the ROM access as well as extension I/O ports capability. This design not only reduces pin count required to access data in ROM dramatically but also allows for systems extension to higher capacity memories while using the existing board design. The application areas include voice, graphic, data storage in consumer products.
2. Features
Data File Mode with only 11 pin interface Sixteen-bit Extension I/O pins with three-state mode Voltage range: 2.4 ~ 3.6V Organization - Memory Cell Array: 4M x 8 Sequential Read Operation in Data File Operation Mode - Sequential Access : 100 ns (min.) at VDD = 3.3V Command/Address/Data Multiplexed I/O port Low Operation Current (Typical) 10 A standby mode current. 30 mA active read current at 100 ns cycle time. Package: bare chip
January 16, 2004
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HF88M32B
3. Functional block diagram
X BUFFER & DECODER Y BUFFER & DECODER CEn OEn WEn MEMORY CELL ARRAY SENSE AMP. CONTROL LOGIC
AC0 AC1 AC2 [A21..A0] RS2..RS0 [P00..P07] [P10..P17]
P0 P1
DIR0 DIR1
[D7.. D0]
4. Pin Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 RS2 RS1 P07 P06 P05 P04 P03 P02 P01 P00 CE GND OE D0 NC D1 NC D2 NC D3 NC HF88M32 NC WE P10 P11 P12 P13 P14 P15 P16 P17 RS0 NC GND NC D7 NC D6 NC D5 NC D4 VCC 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
January 16, 2004
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Symbol RS0~RS2 P07 ~ P00 CEn Pin No. 33, 2, 1

HF88M32B
GND OEn
VCC D7 ~ D0
P17 ~ P10 WEn
I/O Description I Register Select pins RS2 ~ RS0 for accessing ROM data, Address Counter, as well as extension I/O ports. 3 ~ 10 I/O Bi-directional I/O port P0. 11 I The CEn (Chip Enable) input is the device selection and power control for internal Mask ROM array. Whenever CEn goes high, the internal Mask ROM will enter standby (power saving) mode and accesses to internal registers are inhibited. Otherwise, it is in active mode and the contents of the ROM and registers can be accessed. Please note that only accesses to the internal registers are inhibited, but the status of I/O registers are not affected by the CEn pin and will remain unchanged. CEn is also useful to uniquely select a certain device for applications where multiple-chip array is required. 12, 31 P Negative power supply input pin. 13 I OEn (Output Enable) is the output control which gates ROM array data, extension I/O ports, Direction Registers to the data I/O pins D7 ~ D0. The internal Address Counter will automatically increment by one with each rising edge of OEn pin in Sequentially Read mode. 22 P Postive power supply input pin. 14, 16, 18, I/O The Bi-directional Data I/O pins are used to set starting addresses, set the 20, 23, 25, Extension I/O Direction and Output Registers, and to output ROM array 27, 29 data during read operations, contents of I/O Registers and status of input pins. The D7 ~ D7 float to high-impedance when the chip is deselected (CEn high) or when the outputs are disabled. 34 ~ 41 I/O Bi-directional I/O port P1. 42 I WEn controls writing to internal registers such as the Output Port Registers, Direction Registers, Address Counter and Data on D7 ~ D0 are latched on the rising edge of the WE pulse.
January 16, 2004
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HF88M32B
5. Pad Location
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Pad No. Pad Name 1 NC 2 GND 3 RS0 4 P17 5 P16 6 P15 7 P14 8 P13 9 P12 10 P11 11 P10 12 WEN 13 GND 14 NC 15 GND 16 NC 17 GND 18 NC 19 RS2 20 RS1 21 P07 22 P06 23 P05 24 P04 25 P03 26 P02 27 P01 28 P00 29 CEN 30 NC NC: No Connection

HF88M32B
Y Coord. -3262.78 -3039.78 -2816.78 -2593.78 -2370.78 -2140.78 -1917.78 -1687.78 -1464.78 -1234.78 -1011.78 -781.78 -558.78 -335.78 -112.78 110.22 333.22 712.16 935.16 1165.16 1388.16 1618.16 1841.16 2071.16 2294.16 2517.16 2740.16 2963.16 3186.16
Die Size: X= 40130 m, Y=7138 m, and substrate is connected to GND. X Coord. -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 -1941.5 Y Coord. 3231.86 3008.86 2785.86 2562.86 2339.86 2116.86 1893.86 1670.86 1447.86 1224.86 1001.86 778.86 555.86 332.86 -34.78 -257.78 -480.78 -703.78 -926.78 -1149.78 -1372.78 -1595.78 -1818.78 -2041.78 -2264.78 -2487.78 -2710.78 -2931.48 -3152.18 -3372.88 Pad No. Pad Name 31 GND 32 GND 33 GND 34 OEN 35 D0 36 NC 37 D1 38 NC 39 D2 40 NC 41 D3 42 NC 43 VDD 44 GND 45 VDD 46 GND 47 VDD 48 GND 49 D4 50 NC 51 D5 52 NC 53 D6 54 NC 55 D7 56 NC 57 GND 58 GND 59 GND X Coord. 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5 1941.5
6. Device Operation
The device provides the capability of accessing the contents of ROM array by external MCU not through standard address and data bus configuration but through minimal number of 8-bit data bus and control pins. Only 11 pins D7 ~ D0, CEn, OEn, WEn are required to use the device as a Data File device. By fixing the RS2 pin to `0', only CEn, WEn, OEn and D0 ~ D7 are required to access the ROM array data. The CEn pin is device selection pin to uniquely select one device when more than one device are used in parallel and control the access to Mask ROM contents and internal registers. Whenever CEn goes high, the internal Mask ROM will enter standby (power saving) mode and accesses to internal registers are inhibited. Otherwise, it is in active mode. Therefore, when accessing contents of ROM is not intended, the
January 16, 2004 6 V1.11
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CEn pin should be held at `1' to conserve the power consumption.
HF88M32B
In addition to Data File mode, the device also provides the extension I/O capability. Two I/O ports (P0, P1) and total 16 pins are provided. The I/O ports can be configured to function as output pin or high-impedance input pins. Only 14 pins, CEn, WEn, OEn, RS2, RS1, RS0 and D0 ~ D7 are required to provide the Data File function and full access to two I/O ports. There are seven internal registers used to provide the functionality of Data file access as well as Extension I/O capability. These registers are selected by RS2 ~ RS0. All registers are 8-bit wide except AC2. AC2 ~ AC0 are write-only and constitute the complete 22-bit address counter used as pointer to the accessed data. While the I/O ports P0, P1, DIR0 and DIR1 can be read as well as written. Their initial values are as indicated in the following table. When RS2 = `0', the RS1 ~ RS0 are ignored, the address counter can be loaded or contents of Data File can be read. This is to reduce the required pin needed for external MCU to interface with the device and also simplify the procedure for loading the address counter. The P0, P1, DIR0, and DIR1 are used for extension I/O registers. The P0 and P1 are output registers of extension I/O and DIR0 and DIR1 are the direction registers that determine the I/O mode of P0 and P1. Each pin can be configured as output or input mode individually by setting or resetting the corresponding pin of the DIR registers. Initially, both P0 and P1 are default to input mode at `Hi' state. The accesses to the internal registers will be inhibited when CEn is `1'. However, the status of internal registers, such as extension I/O ports, will not be affected. For example, if a certain pin is in output mode and driving `Hi', it will not change when CEn pin goes to `1' state. Therefore, the users are advised to take care of the power down condition of I/O ports when entering sleep mode to prevent unnecessary power drain. RS[2:0] 0xx 100 101 110 111 Symbol AC2 AC1 AC0 P0 DIR0 P1 DIR1 Type R W W W R/W R/W R/W R/W Description Read data by Indirect access Address latch 2 for A21 ~ A16 Address latch 1 for A15 ~ A8 Address latch 0 for A7 ~ A0 Port 0 Output Register Direction Register of Port0 Port 1 Output Register Direction Register of Port1 Initial Value "--------" "--------" "--------" "11111111" "00000000" "11111111" "00000000"
The writing sequence of address counters are AC0 first, AC1 second and AC2 last, once the OEn pin is active to low, and writing pointer of address counter (AC) will be reset to AC0 and always stay at AC0 until the RS2 is set to "0" and WEn pin has a low to high toggle to increase the writing pointer of address counter (AC).
January 16, 2004
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6.1. Retrieve data in Data File
HF88M32B
Accesses to the ROM contents, extension I/O, address counter and direction registers are made through D[7:0] data pins. With register selection pins RS[2:0] set to "0xx", the starting addresses can be written into the address counter through D[7:0] data pins by bringing WEn to low and back to high. The D[7:0] data are latched into the address counter on the rising edge of WEn. Once the starting address of data block is latched into the address counter AC2~0, data can be read out by sequentially pulsing OEn with CEn held low. When CEn is held at `0', the OEn gate the data of the selected address unto Data I/O pin D[7:0]. With the rising edge of OEn, the internal address counter is increased by one automatically.
6.2. Loading the Address Counter
Before the data can be retrieved, the address counter (AC) must be initialized with the starting address, then the contents of ROM pointed to by address counter can be accessed through D[7:0]. In order to simplify the procedure of loading 22-bit address counter (AC), a internal pointer is implemented and used to point to next register to write in the up to three-cycle address loading sequence. Initially, with RS = "0xx" CEn goes from `1' to `0' and the AC pointer is initialized. The pointer is then incremented to point to next register with falling edge of each WEn pulse. So when randomly accessing data within a 256-byte page, or within a 64K-byte block mode, then only one or two-cycle address reload process is needed to access different locations within a page or block. The Address Counter pointer will be held in reset state in the following conditions: 1. 2. When CEn is '1' (the device is deselected). By the Read pulse (OEn is '0') and RS2 = '0' (ROM is being accesses).
The inclusion of the 3rd condition is to force the address loading to start from LSB of Address Counter once the read cycle is initiated. However, the AC Pointer will not be reset when reading or writing from/to extension I/O registers (P0, P1, DIR0, DIR1). This design is useful in certain application scenarios where in the midst of the multi-byte address loading process, an interrupt to the MCU main loop occurs. And in the interrupt service routine, manipulation of extension I/O registers is performed, i.e., key board is scanned using P0 and P1. When the execution of program returns to main loop after interrupt service routine completed, the loading of address can still resume from where it was interrupted.
6.3. Sequential Read Mode and Auto Increment of Address Counter
With each read access to the ROM data (RS = "0xx"), the Address Counter is incremented automatically by one with rising edge of OEn to facility sequential access to a block of ROM data and avoid repeated loading of addresses.
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6.4. Output data to External I/O
HF88M32B
The device's 16-bit Extension I/O capability provides additional I/O ports for applications where the I/O pins are heavily used. To use as a certain pin as output pin, the corresponding bit in Direction Register must be set to `1'. Please refer to the following example where output 0x00 to P0 to `0' is intended. 1. 2. 3. 4. 5. 6. Set RS to "101" (DIR0). Keep D7 ~ D0 at 0xff (all bits in output mode). Pulse the WEn to low then high to write to write contents of D-bus to DIR0. Set RS to "100" (P0 Output Register). Set D7 ~ D0 to 0x00. Pulse the WEn to low then high to write contents of D-bus to P0 and drive all bits in P0 to low.
6.5. Reading Input pin status
To use extension I/O ports as input pins and read the status from them, the corresponding bit in direction register must be set to `0'. Please see the following example where reading inputs from of P1 is intended. 1. 2. 3. 4. 5. 6. Set RS to "111" (DIR1). Set D7 ~ D0 to 0x00h. Pulse the WEn to low then high to set DIR1 to all High-Impedance input modes. Set RS to "110" (P1 Output Register). Pulse the OEn to low. Read P1 then set the OEn back to high.
There is one thing should be noted. For any unused (open) extension I/O pin, it is advisable to set the port to output mode either at `0' or `1' state to prevent it from floating or fix it at VCC or GND if it is set to input mode. Otherwise, the noise might cause the unnecessary power consumption.
6.6. Retrieving the Contents of Extension I/O registers
The contents of all four registers can be read through data bus. The ability to access the contents of registers avoids the necessity of using the RAM as mirror to keep the current status of latches in applications. However, extra care should be taken when reading P0 and P1. To read the contents of P0 and P1, the DIR0 and DIR1 should be set to output mode. Otherwise, the pin status instead of P0 and P1 will be read. The same precaution should be applied in Read-Modify-Write sequence that read back the contents of the output latch of output mode pins and input status of input mode pins.
7. Timing Diagrams
Symbol Parameter TCE Chip selected to active width
January 16, 2004 9
Min. 0
Typ. 50
Max. -
Unit ns
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TWEL TWEH TDHeld TOLZ TACE TOEL TOEH TCEHeld TACER TORL TORH TRCEL TRCEH

100 100 50 200 50 250 150 50 30 100 100 50 50
HF88M32B
ns ns ns ns ns ns ns ns ns ns ns ns ns
WEn active low width WEn inactive low width Written data hold time Read-Write mode transient time ROM data file available time Output enable low duty for access ROM Output enable low duty for access ROM Chip selection signal holding time Register data available time Output enable low duty for access register Output enable low duty for access register RS signal setup time RS signal hold time
7.1.
Data File Read Cycle
tCEHeld tCE tWEL tWEH tOLZ tOEL tOEH
CEn
WEn
OEn tDHeld AC0 D[7:0] Internal Memory Address Internal Memory Data RS[2:0] tRCEL RS2=0, RS1 and RS0 can be any value. 34 AC1 56 AC2 07 ZZ 1E ZZ 3C ZZ 78 ZZ tACE
xxxx34
xx5634
075634 ZZ
075635 ZZ
075636
075637 ZZ tRCEH
1E
3C
78
Data File Read Cycle
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7.2.
CEn

HF88M32B
Interrupted by I/O when Loading Address Counter
WEn
tORL tACER AC0
tORH
OEn
AC1 00h 00h ZZ 55h ZZ BBh 78h
AC2 00h
D[7:0] Internal Memory Address RS[2:0] 000b
3Dh
xxxx3Dh
xx783Dh
00783Dh
101b
111b
100b
110b
000b
P0_Data
FFh
P0_DIR
FFh
00h
P1_Data
FFh
P1_DIR
FFh
00h
Interrupted by I/O when Loading Address Counter
7.3.
CEn
Setting and Reading the I/O Mode for P0 and P1
W En
tO R L tA C E R
tO R H
OEn
D [ 7 :0 ]
F0h
0Fh
F0h
ZZ
0Fh
ZZ
R S [ 2 :0 ]
000b
101b
111b
101b
111b
P 0 _ D a ta
FFh
P 1 _ D a ta
FFh
P 0 _ D IR
00h
F0h
P 1 _ D IR
00h
0Fh
S e t t in g a n d R e a d in g t h e I /O M o d e f o r P 0 a n d P 1
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7.4.
CEn

HF88M32B
Reading P0 and P1 in Mixed-I/O Mode
W En
tO R L tA C E R
tO R H
OEn
D [7 :0 ]
F0h
0Fh
F5h
ZZ
AFh
ZZ
R S [2 :0 ]
000b
101b
111b
100b
110b
P 0 _ D a ta
FFh
P 1 _ D a ta
FFh
P 0 _ D IR
00h
F0h
P 1 _ D IR
00h
0Fh
R e a d in g P 0 a n d P 1 in M ix e d -I /O M o d e
7.5.
CEn
Reading the input pins
W En
OEn
D [7 :0 ]
00h
00h
55h
ZZ
AAh
ZZ
R S [2 :0 ]
000b
101b
111b
100b
110b
P 0 _ D a ta
FFh
P 1 _ D a ta
FFh
P 0 _ D IR
F0h
00h
P 1 _ D IR
0Fh
00h
R e a d in g th e In p u t P in s
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7.6.
CEn

HF88M32B
Output to P0 and P1 Ports
W En
OEn
D [7 :0 ]
FFh
FFh
55h
ZZ
AAh
ZZ
R S [ 2 :0 ]
000b
101b
111b
100b
110b
P 0 _ D a ta
FFh
55h
P 1 _ D a ta
FFh
AAh
P 0 _ D IR
00h
FFh
P 1 _ D IR
00h
FFh
O u tp u t to P 0 a n d P 1 P o r ts
8. Absolute Maximum Rating
Items Supply Voltage Input Voltage Operating Temperature Storage Temperature Symbol VCC VIN TOPR TSTR Rating 2.4 ~ 3.6 V -0.3 to Vdd+0.3 V -0 to 70 C -55 to 125 C
9. AC/DC Electrical Characteristics
(GND = 0V, VCC = 3.0V, TOPR = 25C unless otherwise noted)
Parameter
Supply Voltage Operating Current Standby Current Input voltage Input current leakage P0, P1 Output High Voltage P0, P1 Output Low Voltage D Output High Voltage D Output Low Voltage
Symbol
VCC ICC ISTBY VIH VIL IIL VOH VOL VOH VOL
Min.
2.4 2/3 0 2.4 2.4 -
Typical
30 10 -
Max.
3.6 1 1/3 10 0.4 0.4
Unit
V mA A VCC A V V V V
Condition
No load, tRC@ 100 ns No load VCC = 2.4V ~ 3.6V IOH = 0.3 mA IOL = 2.1 mA IOH = 1.4 mA IOL = 3 mA
January 16, 2004
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HF88M32B
10. Application Circuit Diagram
This application circuit illustrates that how KB83760 MCU uses two external HF88M32Bs for ROM extension as well as keyboard scan functions.
PWMP PWMN COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 RS2 RS1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 U1 C7 C6 C5 C4 C3 C2 C1 CE2n OEn D0 D1 D2 D3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 U2 RS2 RS1 P07 P06 P05 P04 P03 P02 P01 P00 CE VSS OE D0 NC D1 NC D2 NC D3 NC HF88M32 NC WE P10 P11 P12 P13 P14 P15 P16 P17 RS0 NC VSS NC D7 NC D6 NC D5 NC D4 VCC 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 PWMN PWMP WEn R1 R2 R3 R4 R5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 U3 RS2 RS1 P07 P06 P05 P04 P03 P02 P01 P00 CE VSS OE D0 NC D1 NC D2 NC D3 NC HF88M32 NC WE P10 P11 P12 P13 P14 P15 P16 P17 RS0 NC VSS NC D7 NC D6 NC D5 NC D4 VCC 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 WEn
SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19
KB83760
PRT110 PRT111 PRT112 PRT113 PRT114 PRT115 PRT116 PRT117 PRT100 PRT101 PRT102 PRT103 PRT104 PRT105 PRT106 PRT107 PRTC0 PRTC1 PRTC2 PRTC3 PRTC4 PRTC5 PRTC6 PRTC7 PRTD0 PRTD1 PRTD2 PRTD3 PRTD4 PRTD5 PRTD6 PRTD7 KEYTONE SDO DTMFO MUTE VDD SXI SXO TSTP FXI FXO RSTP OPO OPIP OPIN DAO
190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144
PRT110 PRT111 PRT112 PRT113 PRT114 PRT115 PRT116 PRT117 PRT100 PRT101 PRT102 PRT103 PRT104 PRT105 PRT106 PRT107 RS0 RS1 RS2 OEn WEn CE1n CE2n D0 D1 D2 D3 D4 D5 D6 D7 KTONE SDO DTMFO MUTE SXI SXO TSTP FXI FXO RSTP OPO OPIP OPIN DAO VDD VDD
RS0
CE2n OEn D0 D1 D2 D3 VDD
D7 D6 D5 D4
D7 D6 D5 D4 VDD
C7 C6 C5 C4 C3 C2 C1 1 1 1 1 1 1 D1 D2 1N4148 K3 2 2 D3 1N4148 K4 2 D4 1N4148 K5 2 D5 1N4148 K6 2 D6 1N4148 K7 2 M6 K14 M7 K21 M8 K28 M9 K35 M10 1 D7 1N4148
R1 330K
R2 330K
R3 330K
R4 330K
R5 330K
K1 2 1 K8
1N4148 K2
R1
2 K9
3 K10
Auto K11
Erase K12
M1 K13
R2
4 K15
5 K16
6 K17
Pause K18
UP K19
M2 K20
R3
7 K22
8 K23
9 K24
Flash K25
DOWN K26
M3 K27
SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 LC1 LC2 LV1 LV2 LV3 LR4 LR3 LR2 LR1 LR0 LVG GND VO
R4
* K29
0 K30
# K31
Redial K32
Name K33
M4 K34
96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 VO COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 C10 1uF VDD C7 C8 C9 1uF 1uF 1uF C1 1uF C2 1uF C3 1uF C4 1uF C5 1uF C6 1uF R5
PGM
Mute
HF
HOLD
Dial
M5
January 16, 2004
14
V1.11
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd

HF88M32B
11. Updated History
Version 1.10 1.11 Date 2003/8/27 2004/1/16 Update Description Timing diagrams modified. Add the die size.
January 16, 2004
15
V1.11
This specification is subject to change without notice. Please contact sales person for the latest version before use.

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